From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise., , и . NATW, стр. 61-64. IEEE, (2014)Pseudo Functional Path Delay Test through Embedded Memories., , , , и . J. Electron. Test., 31 (1): 35-42 (2015)IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays., , и . IEEE Trans. Computers, 47 (10): 1136-1152 (1998)Mixed structural-functional path delay test generation and compaction., , , и . DFTS, стр. 7-12. IEEE Computer Society, (2013)Challenges in Delay Testing of Integrated Circuits.. DFT, стр. 81-82. IEEE Computer Society, (2009)Maximizing crosstalk-induced slowdown during path delay test., и . ICCD, стр. 159-166. IEEE Computer Society, (2012)Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages., и . ITC, стр. 767-775. IEEE Computer Society, (1996)Levelized low cost delay test compaction considering IR-drop induced power supply noise., , , и . VTS, стр. 52-57. IEEE Computer Society, (2011)IDDQ Test: Will It Survive the DSM Challenge?, и . IEEE Des. Test Comput., 19 (5): 8-16 (2002)An efficient solution to the storage correspondence problem for large sequential circuits., , и . ASP-DAC, стр. 181-186. ACM, (2001)