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Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators.

, , и . ISVLSI, стр. 240-245. IEEE, (2020)

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Anshul Sawant

Anshul Bhardwaj

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Anshul Gupta

Rohini Kumar

 

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Built-in Self Test Based on Multiple On-Chip Signature Checking., , и . J. Electron. Test., 14 (3): 227-244 (1999)A SysML Profile for Development and Early Validation of TLM 2.0 Models., , и . ECMFA, том 6698 из Lecture Notes in Computer Science, стр. 299-311. Springer, (2011)PLSS: A Scheduler for Multi-core Embedded Systems., , и . ARCS, том 10172 из Lecture Notes in Computer Science, стр. 164-176. Springer, (2017)Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units., , , и . SCOPES, том 3199 из Lecture Notes in Computer Science, стр. 17-32. Springer, (2004)A scheme for multiple on-chip signature checking for embedded SRAMS., , и . J. Syst. Archit., 46 (2): 181-199 (2000)Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators., , и . ISVLSI, стр. 240-245. IEEE, (2020)VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (11): 4252-4265 (2020)Exploring Storage Organization in ASIP Synthesis., , и . DSD, стр. 120-127. IEEE Computer Society, (2003)Application Specific Datapath Extension with Distributed I/O Functional Units., , и . VLSI Design, стр. 551-558. IEEE Computer Society, (2007)On-Chip Signature Checking for Embedded Memories., , и . VLSI Design, стр. 558-563. IEEE Computer Society, (1998)