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Другие публикации лиц с тем же именем

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip., , , и . Embedded Systems Design and Verification, CRC Press, (2009)Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip., , , и . ACM Great Lakes Symposium on VLSI, стр. 125-128. ACM, (2009)Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels., и . AISTECS@HiPEAC, стр. 12-17. ACM, (2017)Interdisciplinary design of a research experience on microelectronic systems for K-12 students., и . EWME, стр. 64-69. IEEE, (2014)Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis., , , и . DATE, стр. 1589-1594. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Power aware network interface management for streaming multimedia., , и . WCNC, стр. 926-930. IEEE, (2002)An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing., и . DCIS, стр. 1-6. IEEE, (2019)Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform., , и . VLSI-SoC (Selected Papers), том 621 из IFIP Advances in Information and Communication Technology, стр. 87-112. Springer, (2020)Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip., , , и . IET Comput. Digit. Tech., (2013)DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost., , , и . ARC, том 9040 из Lecture Notes in Computer Science, стр. 419-426. Springer, (2015)