( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Visualization of Partial Order Models in VLSI Design Flow.

, , и . DATE, стр. 1089. IEEE Computer Society, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Evgenia Bystrov

V Saile

V Geoffroy

V Wittwer

V Ustinov

 

Другие публикации лиц с тем же именем

Synthesis of Asynchronous Circuits with Predictable Latency., и . IWLS, стр. 239-243. (2002)STG Optimisation in the Direct Mapping of Asynchronous Circuits ., , и . DATE, стр. 10932-10939. IEEE Computer Society, (2003)Phase-Encoding for On-Chip Signalling., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (2): 535-545 (2008)Implementing Model Checking and Equivalence Checking for Time Petri Nets by the RT-MEC Tool., и . PaCT, том 1662 из Lecture Notes in Computer Science, стр. 194-199. Springer, (1999)Petri Net Modelling of Estelle-specified Communication Protocols., , , , , и . PaCT, том 964 из Lecture Notes in Computer Science, стр. 94-108. Springer, (1995)Design and Analysis of a Self-Timed Duplex Communication System., , , и . IEEE Trans. Computers, 53 (7): 798-814 (2004)On-chip structures for timing measurement and test., , , , и . Microprocess. Microsystems, 27 (9): 473-483 (2003)Selected Articles from the IEEE LPonTR 2012 Workshop.. J. Low Power Electron., 9 (1): 118 (2013)Application of Modified Coloured Petri Nets to Modeling and Verification of SDL Specified Communication Protocols., , , , , , , , и . CSR, том 4649 из Lecture Notes in Computer Science, стр. 303-314. Springer, (2007)A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits., , , , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 471-480. Springer, (2004)