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Analyzing power efficiency of optimization techniques and algorithm design methods for applications on heterogeneous platforms., , , , и . Int. J. High Perform. Comput. Appl., 28 (3): 319-334 (2014)MGSim + MGMark: A Framework for Multi-GPU System Research., , , , , , , , , и 3 other автор(ы). CoRR, (2018)AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators., , , , , , , , и . CGO, стр. 143-157. IEEE, (2024)Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching., , и . PDPTA, стр. 819-823. CSREA Press, (2003)Source level transformations to improve I/O data partitioning., и . SNAPI@PACT, стр. 27-35. ACM, (2003)Message from the Program Chairs : IISWC 2020., и . IISWC, стр. x-xi. IEEE, (2020)WBT-2000: workshop on binary translation - 2000., и . SIGARCH Comput. Archit. News, 29 (1): 23-25 (2001)Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA., , , , и . SIGARCH Comput. Archit. News, 43 (4): 52-57 (2015)Virtual machine monitor-based lightweight intrusion detection., , , , , и . ACM SIGOPS Oper. Syst. Rev., 45 (2): 38-53 (2011)Obtaining FPGA soft error rate in high performance information systems., , , и . Microelectron. Reliab., 49 (5): 551-557 (2009)