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Constant voltage electromigration for advanced BEOL copper interconnects., , , , , , , и . IRPS, стр. 2. IEEE, (2015)Impact of process variability on BEOL TDDB lifetime model assessment., , , , и . IRPS, стр. 5. IEEE, (2015)Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow., , , , и . VLSI-SOC, стр. 34-39. IEEE, (2020)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects., , , , , , , , , и 1 other автор(ы). Microelectron. Reliab., (2017)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies., , , , , , , , , и 6 other автор(ы). ESSDERC, стр. 102-105. IEEE, (2014)Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation., , , , , и . Microelectron. Reliab., (2016)3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs., , , , и . VLSI-SoC (Selected Papers), том 621 из IFIP Advances in Information and Communication Technology, стр. 279-300. Springer, (2020)Intrinsic reliability of local interconnects for N7 and beyond., , , , , , , , , и 1 other автор(ы). IRPS, стр. 2. IEEE, (2015)Design Technology co-optimization for N10., , , , , , , , , и 18 other автор(ы). CICC, стр. 1-8. IEEE, (2014)Integration of a Stacked Contact MOL for Monolithic CFET., , , , , , , , , и 13 other автор(ы). VLSI Technology and Circuits, стр. 1-2. IEEE, (2023)