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A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS.

, , , , , , , , , , и . ISSCC, стр. 270-271. IEEE, (2008)

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Sreedhar Madishetti

Kasyap Natarajan

Paruthiure Natarajan

Natarajan Thiagarajan

Balamurali Sreedhar

 

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Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI., и . ASP-DAC/VLSI Design, стр. 297-298. IEEE Computer Society, (2002)Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology., , , , , , , , и . ISSCC, стр. 224-225. IEEE, (2013)A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 270-271. IEEE, (2008)A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 332-333. IEEE, (2014)Leakage Reduction techniques in a 0.13um SRAM Cell., , , и . VLSI Design, стр. 215-221. IEEE Computer Society, (2004)A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 316-317. IEEE, (2013)A high density, low leakage, 5T SRAM for embedded caches., , , и . ESSCIRC, стр. 215-218. IEEE, (2004)Semantic Information Integration and Processing for Demand Response Optimization, , , и . Southern California Smart Grid Research Symposium (SoCalSGS), (2011)Poster.A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash., , , , , , , , , и 3 other автор(ы). VLSI-DAT, стр. 1-4. IEEE, (2013)