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Другие публикации лиц с тем же именем

Performance Limits of Trace Caches., , и . J. Instruction-Level Parallelism, (1999)An Overview of Static Pipelining., , , и . IEEE Comput. Archit. Lett., 11 (1): 17-20 (2012)Memory Renaming: Fast, Early and Accurate Processing of Memory Communication., и . Int. J. Parallel Program., 27 (5): 357-380 (1999)Program Differentiation., , , , и . Journal of Circuits, Systems, and Computers, (2012)Evaluating the Effects of Predicated Execution on Branch Prediction., и . Int. J. Parallel Program., 24 (2): 159-186 (1996)Amniote: A User Space Interface to the Android Runtime., и . ENASE, стр. 59-67. SciTePress, (2019)Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache., , и . MICRO, стр. 433-444. IEEE Computer Society, (2007)Analyzing the Working Set Characteristics of Branch Execution., и . MICRO, стр. 49-58. ACM/IEEE Computer Society, (1998)Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows., , и . MICRO, стр. 19-29. IEEE Computer Society, (2005)Improving BTB performance in the presence of DLLs., , и . MICRO, стр. 77-86. ACM/IEEE Computer Society, (2000)