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Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)., , , , , , , и . IEICE Trans. Electron., 91-C (5): 731-735 (2008)Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality., , , , , , , , , и . Neurocomputing, (2021)Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect., , , , и . ISCE, стр. 1-2. IEEE, (2015)Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array., , , , , , , , и . IEEE Access, (2021)Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks., , , , , , , и . Adv. Intell. Syst., 3 (8): 2100064 (2021)Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance., , , , , и . IEICE Electron. Express, 9 (9): 828-833 (2012)Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory., , , , , и . IEICE Trans. Electron., 92-C (5): 659-663 (2009)Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices., , , , , , , и . IEICE Trans. Electron., 90-C (5): 988-993 (2007)Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)., , , , , и . IEICE Trans. Electron., 92-C (5): 620-626 (2009)A Spiking Neural Network with a Global Self-Controller for Unsupervised Learning Based on Spike-Timing-Dependent Plasticity Using Flash Memory Synaptic Devices., , , , , , и . IJCNN, стр. 1-7. IEEE, (2019)