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Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.

, , , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (9): 1621-1633 (2012)

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Xiaoyu Qiang

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Xu Xu

Wenjiang Qiang

You Qiang

 

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