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On Efficiently and Reliably Achieving Low Defective Part Levels.

, , и . ITC, стр. 616-625. IEEE Computer Society, (1995)

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Delay Testing Quality in Timing-Optimized Designs., , , и . ITC, стр. 897-905. IEEE Computer Society, (1991)Effect of Record Length on Noise-Induced Error in the Cross Correlation Estimate., , и . IEEE Trans. Syst. Man Cybern., 2 (2): 255-261 (1972)A weighted random pattern test generation system., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (8): 1020-1025 (1996)Design of testable logic circuits.. Proc. IEEE, 74 (3): 525 (1986)Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects., , , , , , и . ITC, стр. 1041-1050. IEEE Computer Society, (2003)Tester retargetable patterns., и . ITC, стр. 721-727. IEEE Computer Society, (2001)Design for Testability: The Path to Deep Submicron.. Asian Test Symposium, IEEE Computer Society, (2005)Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture., , , и . DATE, стр. 10110-10115. IEEE Computer Society, (2003)Directed-Binary Search in Logic BIST Diagnostics., , и . DATE, стр. 1121. IEEE Computer Society, (2002)Fast seed computation for reseeding shift register in test pattern compression., , и . ICCAD, стр. 76-81. ACM / IEEE Computer Society, (2002)