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A Hybrid Power Model for RTL Power Estimation., , , , и . ASP-DAC, стр. 551-556. IEEE, (1998)Estimation for maximum instantaneous current through supply lines for CMOS circuits., , и . IEEE Trans. Very Large Scale Integr. Syst., 8 (1): 61-73 (2000)A method of batching conflict routings in shuffle-exchange networks., , , и . Theor. Comput. Sci., (2014)Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble., , , , , , , и . ISPD, стр. 195-202. ACM, (2022)Delay testing considering power supply noise effects., , и . ITC, стр. 181-190. IEEE Computer Society, (1999)Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices., и . DAC, стр. 760-765. ACM Press, (1999)Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 756-769 (2003)Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (3): 416-425 (2001)A Power Network Synthesis Method for Industrial Power Gating Designs., , и . ISQED, стр. 362-367. IEEE Computer Society, (2007)VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs., , и . ISLPED, стр. 156-161. ACM, (1999)