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Pre-Defined Sparse Neural Networks With Hardware Acceleration., , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 9 (2): 332-345 (2019)Slack matching mode-based asynchronous circuits for average-case performance., и . ICCAD, стр. 219-225. IEEE, (2013)A memory allocation and assignment method using multiway partitioning., , и . SoCC, стр. 143-144. IEEE, (2004)High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog., и . CPA, том 63 из Concurrent Systems Engineering Series, стр. 275-288. IOS Press, (2005)SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces., и . CPA, том 68 из Concurrent Systems Engineering Series, стр. 287-302. IOS Press, (2011)Toward Efficient Hyperspectral Image Processing inside Camera Pixels., , , , и . CoRR, (2022)qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit., , , и . CoRR, (2020)Towards a Formal Treatment of Logic Locking., , , , и . IACR Cryptol. ePrint Arch., (2022)Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template., и . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 838-849 (2014)Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 13 (4): 448-461 (2005)