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Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory., , , и . ICECS, стр. 123-124. IEEE, (2019)Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework., , , , , , и . Integr., (2020)A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion., , , , и . CoRR, (2022)STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications., , , и . LASCAS, стр. 1-4. IEEE, (2023)Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers., , , и . ASICON, стр. 1-4. IEEE, (2019)Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification., , , , , , , и . IEEE Access, (2022)Fast computation of Cramer-Rao Bounds for TOA., , , и . LA-CCI, стр. 1-6. IEEE, (2016)EDAM: edit distance tolerant approximate matching content addressable memory., , , , , и . ISCA, стр. 495-507. ACM, (2022)Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs., , , , , , и . SMACD, стр. 85-88. IEEE, (2019)Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories., , , , и . LASCAS, стр. 1-4. IEEE, (2022)