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A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . ISSCC, стр. 378-380. IEEE, (2019)

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Yun-sang Kim

Sang Kyu Kim

Moo Sang Kim

Oh-Sang Kim

Sang-Kyum Kim

 

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Local Wavelets Decomposition for 3-D Surfaces., , , и . ICIP (4), стр. 357-360. IEEE, (1999)Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks., , , , , и . ASYNC, стр. 48-54. IEEE, (2021)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques., , , , , , , , , и 18 other автор(ы). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)A Multiresolution Wavelet Scheme for Irregularly Subdivided 3D Triangular Mesh., , , , и . ICIP (1), стр. 171-174. IEEE, (1999)Adaptive wavelets based multiresolution modeling of irregular meshes via harmonic maps., , и . ICIP (3), стр. 210-213. IEEE, (2001)11-Bit 1.8uW 40KS/s segmented SAR ADC for sensor applications., , и . ISOCC, стр. 55-56. IEEE, (2016)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , и 20 other автор(ы). ISSCC, стр. 378-380. IEEE, (2019)22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process., , , , , , , , , и 29 other автор(ы). ISSCC, стр. 382-384. IEEE, (2020)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , и 5 other автор(ы). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)An Ultra Low Power, 3-Wire Serial Interface Design for Data Converters in Pin-Constrainted Applications with 180 nm CMOS Technology., , , , и . FIT, стр. 104-109. IEEE Computer Society, (2017)