( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip.

, , , и . ICRC, стр. 1-11. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Tushar Krishna

Tushar Khandeparkar

Tushar Chaudhuri

Tushar Gosavi

Tushar Chatterjee

 

Другие публикации лиц с тем же именем

ASTRA-SIM: Enabling SW/HW Co-Design Exploration for Distributed DL Training Platforms., , , и . ISPASS, стр. 81-92. IEEE, (2020)Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures., , , , , , , и . ASP-DAC, стр. 197-203. ACM, (2021)Extending Sparse Tensor Accelerators to Support Multiple Compression Formats., , , , , , , , , и . IPDPS, стр. 1014-1024. IEEE, (2021)Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip., , , и . ICRC, стр. 1-11. IEEE, (2018)Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics., , , , , и . VLSI-SOC, стр. 123-128. IEEE, (2020)AIrchitect: Automating Hardware Architecture and Mapping Optimization., , и . DATE, стр. 1-6. IEEE, (2023)Heterogeneous Dataflow Accelerators for Multi-DNN Workloads., , , , , и . HPCA, стр. 71-83. IEEE, (2021)RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU., , , , , , и . DAC, стр. 253-258. IEEE, (2021)Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML., , , и . DAC, стр. 583-588. ACM, (2022)Themis: a network bandwidth-aware collective scheduling policy for distributed training of DL models., , , , и . ISCA, стр. 581-596. ACM, (2022)