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RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model., , , и . CoRR, (2023)The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models., , , , , , , , , и 24 other автор(ы). CoRR, (2024)RouteNet: routability prediction for mixed-size designs using convolutional neural network., , , , , , и . ICCAD, стр. 80. ACM, (2018)Robustify ML-Based Lithography Hotspot Detectors., , , , и . ICCAD, стр. 134:1-134:7. ACM, (2022)Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization., , , и . CoRR, (2024)CAMU-Net: Copy-move forgery detection utilizing coordinate attention and multi-scale feature fusion-based up-sampling., , , , , , и . Expert Syst. Appl., 238 (Part C): 121918 (марта 2024)Preplacement Net Length and Timing Estimation by Customized Graph Neural Network., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4667-4680 (2022)The Dark Side: Security Concerns in Machine Learning for EDA., , , и . CoRR, (2022)RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution., , , , , и . CoRR, (2023)FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs., , , , и . FPGA, стр. 15-25. ACM, (2023)