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A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process., и . IEEE Trans. Biomed. Circuits Syst., 10 (6): 1087-1099 (2016)Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs., , , и . IEEE J. Solid State Circuits, 46 (2): 537-545 (2011)Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits., , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process., и . VLSI-DAT, стр. 1-4. IEEE, (2013)New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process., и . VLSI-DAT, стр. 1-4. IEEE, (2012)Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology., и . SoCC, стр. 33-36. IEEE, (2013)Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits., и . ISCAS (1), стр. 297-300. IEEE, (2003)Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS., и . CICC, стр. 689-696. IEEE, (2009)Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices., и . CICC, стр. 539-542. IEEE, (2009)Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications., и . MWSCAS, стр. 1-4. IEEE, (2018)