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A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator., , , и . SoCC, стр. 39-42. IEEE, (2009)Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC., , , и . ISCAS, стр. 1-5. IEEE, (2018)A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier., , , , и . ISCAS, стр. 1-4. IEEE, (2017)An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC., , , , и . APCCAS, стр. 18-21. IEEE, (2018)A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation., , , , и . ASICON, стр. 686-689. IEEE, (2017)A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC., , , , и . ASICON, стр. 1-4. IEEE, (2013)A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic., , , и . APCCAS, стр. 42-45. IEEE, (2018)A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC., , , , и . ASICON, стр. 1-4. IEEE, (2019)An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration., , и . Microelectron. J., (2018)A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation., , , , и . APCCAS, стр. 128-131. IEEE, (2012)