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Другие публикации лиц с тем же именем

Efficient BDD-based Fault Simulation in Presence of Unknown Values., , , , и . Asian Test Symposium, стр. 383-388. IEEE Computer Society, (2011)Autonomous Testing for 3D-ICs with IEEE Std. 1687., , , и . ATS, стр. 215-220. IEEE Computer Society, (2016)Test Set Stripping Limiting the Maximum Number of Specified Bits., , , и . DELTA, стр. 581-586. IEEE Computer Society, (2008)Optimized Selection of Frequencies for Faster-Than-at-Speed Test., , , , , и . ATS, стр. 109-114. IEEE Computer Society, (2015)Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses., , , , и . ITC, стр. 1-10. IEEE, (2019)Built-In Test for Hidden Delay Faults., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1956-1968 (2019)Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead., , и . ETS, стр. 53-58. IEEE Computer Society, (2009)Power-aware test generation with guaranteed launch safety for at-speed scan testing., , , , , , , и . VTS, стр. 166-171. IEEE Computer Society, (2011)An on-chip self-test architecture with test patterns recorded in scan chains., , и . ITC, стр. 1-10. IEEE, (2016)Efficient fault simulation on many-core processors., , , и . DAC, стр. 380-385. ACM, (2010)