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Verification and synthesis of counters based on symbolic techniques., , , и . ED&TC, стр. 176-181. IEEE Computer Society, (1997)Symbolic traversals of data paths with auxiliary variables., , и . Great Lakes Symposium on VLSI, стр. 93-96. IEEE, (1994)Interpolation with Guided Refinement: Revisiting incrementality in SAT-based unbounded model checking., , и . FMCAD, стр. 43-50. IEEE, (2014)Tightening BDD-based approximate reachability with SAT-based clause generalization∗., , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)Cross-fertilizing FSM verification techniques and sequential diagnosis., , , , и . EURO-DAC, стр. 306-311. IEEE Computer Society Press, (1992)SAT solver management strategies in IC3: an experimental approach., , , , и . Formal Methods Syst. Des., 50 (1): 39-74 (2017)Thread-based multi-engine model checking for multicore platforms., , и . ACM Trans. Design Autom. Electr. Syst., 18 (3): 36:1-36:28 (2013)Interpolation sequences revisited., , и . DATE, стр. 316-322. IEEE, (2011)Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking., , , и . DATE, стр. 688-689. IEEE Computer Society, (2005)Trading-Off SAT Search and Variable Quantifications for Effective Unbounded Model Checking., , , , , и . FMCAD, стр. 1-8. IEEE, (2008)