( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.

, , , , , , , , , , , , , , , и . ASP-DAC, стр. 369-370. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Hideharu Umehara

Kyoko Amano

Yu Amano

Shun'ichi Amano

 

Другие публикации лиц с тем же именем

A Routing Algorithm for DS-WDM Ring., , и . Applied Informatics, стр. 562-565. IASTED/ACTA Press, (1999)Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism., , , , , и . PDPTA, стр. 1148-1154. CSREA Press, (2003)A Packet Forwarding Layer for DIMMnet and its Hardware Implementation., , , , , и . PDPTA, стр. 461-467. CSREA Press, (2005)Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips., , и . PDPTA, стр. 1343-1349. CSREA Press, (2005)A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory., , , , , и . Parallel and Distributed Computing and Systems, стр. 68-71. IASTED/ACTA Press, (1995)Total System Image of the Reconfigurable Machine WASMII., , , , и . PDPTA, стр. 1092-1096. CSREA Press, (1997)Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot., , , , , и . PDPTA, стр. 787-793. CSREA Press, (2007)Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot., , , , , , и . Clust. Comput., 5 (1): 7-17 (2002)A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface., , , , , , , , , и 1 other автор(ы). IEEE Micro, 33 (6): 6-15 (2013)A Scalable Body Bias Optimization Method Toward Low-Power CGRAs., , , и . IEEE Micro, 43 (1): 49-57 (2023)