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On-die decoupling capacitance: frequency domain analysis of activity radius., , , и . ISCAS, IEEE, (2006)Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects., , , и . VLSI-SOC, стр. 99-104. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Timing optimization in logic with interconnect., , , и . SLIP, стр. 19-26. ACM, (2008)Networks on chips: keeping up with Rent's rule and Moore's law.. SLIP, стр. 55-56. ACM, (2007)Task Scheduling Based On Thread Essence and Resource Limitations., , и . J. Comput., 7 (1): 53-64 (2012)Design and dynamic management of hierarchical NoCs., , и . Microprocess. Microsystems, (2016)Optimal resizing of bus wires in layout migration., , и . ICECS, стр. 411-414. IEEE, (2004)Crosstalk noise reduction in synthesized digital logic circuits., и . IEEE Trans. Very Large Scale Integr. Syst., 11 (6): 1153-1158 (2003)Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing., , и . Hot Interconnects, стр. 41-48. IEEE Computer Society, (2014)Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors., , и . PAAP, стр. 65-72. IEEE Computer Society, (2010)