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Realizing High Test Quality Goals with Smart Test Resource Usage.

, , , , , , , и . ITC, стр. 525-533. IEEE Computer Society, (2004)

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Janusz Panzer

Janusz Rat

Janusz Gatniejewski

Janusz Surzykiewicz

Janusz Bogdanowicz

 

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Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits., и . ITC, стр. 473-482. IEEE Computer Society, (1991)On Using Implied Values in EDT-based Test Compression., , , , и . DAC, стр. 11:1-11:6. ACM, (2014)2D Test Sequence Generators., , и . IEEE Des. Test Comput., 20 (1): 51-59 (2003)Embedded Deterministic Test for Low-Cost Manufacturing., , , , , и . IEEE Des. Test Comput., 20 (5): 58-66 (2003)GEMINI-a logic system for fault diagnosis based on set functions.. FTCS, стр. 292-297. IEEE Computer Society, (1988)Hardware Protection via Logic Locking Test Points., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3020-3030 (2018)EDT Bandwidth Management in SoC Designs., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1894-1907 (2012)Embedded deterministic test., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 776-792 (2004)Low Cost Hypercompression of Test Data., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2964-2975 (2020)On necessary and nonconflicting assignments in algorithmic test pattern generation., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (4): 515-530 (1994)