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IBM POWER8 performance and energy modeling.

, , , , , , , , , , , и . IBM J. Res. Dev., (2015)

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Jörg Eickemeyer

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Walter Eickemeyer

Georg Eickemeyer

Walter Eickemeyer

 

Другие публикации лиц с тем же именем

A performance methodology for commercial servers., , , , , , , , и . IBM J. Res. Dev., 44 (6): 851-872 (2000)Instruction-level parallelism from execution interlock collapsing., , и . SIGARCH Comput. Archit. News, 20 (4): 38-43 (1992)Performance Evaluation of Multiple Register Sets., и . ISCA, стр. 264-271. (1987)Performance Evaluation of On-Chip Register and Cache Organizations., и . ISCA, стр. 64-72. IEEE Computer Society, (1988)On the attributes of the SCISM organization., , и . SIGARCH Comput. Archit. News, 20 (4): 44-53 (1992)IBM POWER8 performance and energy modeling., , , , , , , , , и 2 other автор(ы). IBM J. Res. Dev., (2015)Performance Evaluation of Multiple Register Set Architectures and Cache Memories. University of Illinois Urbana-Champaign, USA, (1988)Interlock collapsing ALU for increased instruction-level parallelism., , и . MICRO, стр. 149-157. ACM / IEEE Computer Society, (1992)Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors., , , , , , , , , и 1 other автор(ы). HPCA, стр. 238-242. IEEE Computer Society, (2005)POWER5 system microarchitecture., , , , и . IBM J. Res. Dev., 49 (4-5): 505-522 (2005)