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Low-Density Parity-Check Code Decoder Design and Error Characterization on an FPGA Based Framework.. University of Arizona, Tucson, USA, (2019)base-search.net (ftunivarizona:oai:repository.arizona.edu:10150/633122).Accelerated Shadow Detection and Removal Method., , , , , и . AICCSA, стр. 1-8. IEEE Computer Society, (2019)Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes., , , , и . ReConFig, стр. 1-8. IEEE, (2019)Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization., и . FPL, стр. 1-8. IEEE, (2016)Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 3074-3084 (2018)Efficient FPGA implementation of probabilistic gallager B LDPC decoder., , , , , и . ICECS, стр. 178-181. IEEE, (2017)Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder., , , , и . NEWCAS, стр. 333-336. IEEE, (2017)Identification of Cancer Patient Subgroups via Smoothed Shortest Path Graph Kernel., и . CoRR, (2016)ESCAPED: Efficient Secure and Private Dot Product Framework for Kernel-based Machine Learning Algorithms with Applications in Healthcare., , и . CoRR, (2020)ppAUC: Privacy Preserving Area Under the Curve with Secure 3-Party Computation., , и . CoRR, (2021)