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Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization.

J. Lee, J. Park, S. Kim, и H. Jeong. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 4949-4961 (декабря 2023)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

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Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM.J. Park, S. Lee, и H. Jeong. IEEE Trans. Circuits Syst. I Regul. Pap., 70 (2): 797-805 (февраля 2023)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_MIN$ Improvement and Energy Saving.H. Jeong, S. Oh, T. Oh, H. Kim, C. Park, W. Rim, T. Song, и S. Jung. IEEE J. Solid State Circuits, 54 (3): 896-906 (2019)Power-Gated 9T SRAM Cell for Low-Energy Operation.T. Oh, H. Jeong, K. Kang, J. Park, Y. Yang, и S. Jung. IEEE Trans. Very Large Scale Integr. Syst., 25 (3): 1183-1187 (2017)Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter.T. Na, H. Jeong, S. Jung, J. Kim, и S. Kang. ICECS, стр. 400-403. IEEE, (2015)Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.J. Lee, H. Jeong, Y. Yang, J. Kim, и S. Jung. ISOCC, стр. 479-482. IEEE, (2012)Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead.H. Park, и H. Jeong. IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1728-1738 (2022)Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits.H. Jeong, Y. Yang, J. Lee, J. Kim, и S. Jung. ICECS, стр. 833-836. IEEE, (2012)Pseudo NMOS based sense amplifier for high speed single-ended SRAM.H. Jeong, T. Kim, S. Jung, T. Song, и G. Kim. ICECS, стр. 331-334. IEEE, (2014)Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.H. Jeong, J. Park, T. Oh, W. Rim, T. Song, G. Kim, H. Won, и S. Jung. IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1059-1063 (2016)A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology.I. Lee, H. Jeong, S. Baeck, S. Gupta, C. Park, D. Seo, J. Choi, J. Kim, H. Kim, J. Kang и 9 other автор(ы). ISSCC, стр. 392-394. IEEE, (2019)

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