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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization., , , , , , , , , и 2 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 440-448 (2022)Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength., , и . ACM Great Lakes Symposium on VLSI, стр. 399-404. ACM, (2020)AES design improvement towards information safety., , , , , , , и . ISCAS, стр. 1706-1709. IEEE, (2016)OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits., , , , и . ICCAD, стр. 1-9. IEEE, (2023)PDG: A Prefetcher for Dynamic Graph Updating., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1246-1259 (апреля 2024)ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY., , , , и . ICCAD, стр. 118. ACM, (2016)DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache., , , , и . ISQED, стр. 408-414. IEEE, (2020)TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning., , , , , , и . DAC, стр. 1-6. IEEE, (2023)Quantitative evaluation of reliability and performance for STT-MRAM., , , , , , и . ISCAS, стр. 1150-1153. IEEE, (2016)Architecture design with STT-RAM: Opportunities and challenges., , , , , и . ASP-DAC, стр. 109-114. IEEE, (2016)