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System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic., , , и . VLSI-SoC, стр. 308-313. IEEE, (2011)Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches., , и . NoCArc@MICRO, стр. 31-36. ACM, (2009)Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints., , , , , , , и . DATE, стр. 562-565. IEEE, (2009)Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip., , , и . ACM Great Lakes Symposium on VLSI, стр. 125-128. ACM, (2009)Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels., , , и . MCSoC, стр. 159-166. IEEE Computer Society, (2012)A library of dual-clock FIFOs for cost-effective and flexible MPSoC design., , и . ICSAMOS, стр. 20-27. IEEE, (2010)Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs., , , , и . DATE, стр. 679-684. IEEE Computer Society, (2010)Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology., , , , и . NoCArc@MICRO, стр. 37-42. ACM, (2010)On the maximum achievable rates in wireless meshed networks: centralized versus decentralized solutions., , и . ICASSP (4), стр. 573-576. IEEE, (2004)A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs., , , , , , , , и . ACM Trans. Embed. Comput. Syst., 12 (4): 106:1-106:29 (2013)