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A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement., , , , , , , и . A-SSCC, стр. 1-3. IEEE, (2021)Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer., , , , , , и . IEEE Access, (2020)8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation., , , , , , и . IEEE Access, (2024)A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 909-913 (2022)A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4043-4047 (2022)A 3.2-GHz 178-fsrms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier., , , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 30 (7): 915-925 (2022)A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations., , , , , , и . IEEE Access, (2020)A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator., , , , , , , и . Sensors, 21 (20): 6824 (2021)Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems., , , , , , , и . Sensors, 20 (8): 2430 (2020)