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3D clock distribution using vertically/horizontally-coupled resonators.

, , , и . ISSCC, стр. 258-259. IEEE, (2013)

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Heinrich Take

Yasuhiro Murakawa

Ingo Take

Yasuhiro Arahata

Yasuhiro Shirasaki

 

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Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer., , , , , , , , и . VLSIC, стр. 82-. IEEE, (2015)Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface., , , , и . ASP-DAC, стр. 44-45. IEEE, (2015)Design and analysis for ThruChip design for manufacturing (DFM)., , , , , и . ASP-DAC, стр. 46-47. IEEE, (2015)Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration., , , и . IEICE Trans. Electron., 98-C (4): 288-297 (2015)3D clock distribution using vertically/horizontally-coupled resonators., , , и . ISSCC, стр. 258-259. IEEE, (2013)Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links., , , , , , , , , и 1 other автор(ы). FPL, стр. 1. IEEE, (2013)Low-latency wireless 3D NoCs via randomized shortcut chips., , , , , , , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs., , , , и . IEICE Trans. Inf. Syst., 96-D (12): 2753-2764 (2013)A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel., , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2584-2591 (2015)A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking., , , , и . ISSCC, стр. 490-492. IEEE, (2011)