( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology.

, , , , и . DDECS, стр. 40-45. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Juraj Kukolja

Juraj Kukolja

Juraj Böhm

Juraj Mészáro

Juraj Slovak

 

Другие публикации лиц с тем же именем

Numerical method for DC fault analysis simplification and simulation time reduction., , и . DDECS, стр. 170-174. IEEE Computer Society, (2013)Increasing the efficiency of analog OBIST using on-chip compensation of technology variations., , , и . DDECS, стр. 71-74. IEEE Computer Society, (2011)Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation., , и . DDECS, стр. 293-298. IEEE Computer Society, (2008)Impedance calculation based method for AC fault analysis of mixed-signal circuits., , , и . DDECS, стр. 74-79. IEEE, (2016)A novel impedance calculation method and its time efficiency evaluation., , , , и . DDECS, стр. 99-103. IEEE Computer Society, (2014)Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies., , , и . DDECS, стр. 395-396. IEEE Computer Society, (2011)Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology., , , , и . DDECS, стр. 40-45. IEEE, (2016)BIST architecture for oscillation test of analog ICs and investigation of test hardware influence., , , , , и . Microelectron. Reliab., 54 (5): 985-992 (2014)A Novel Method Towards Time-Efficient Fault Analysis of Analog and Mixed-Signal Circuits., , , , , и . J. Circuits Syst. Comput., 26 (8): 1740005:1-1740005:20 (2017)Application of IDDT test towards increasing SRAM reliability in nanometer technologies., , , и . DDECS, стр. 167-170. IEEE, (2012)