( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A Skew-Normal Canonical Model for Statistical Static Timing Analysis.

, , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2359-2368 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Ramaswami Vasudevan

N Vasudevan

Desikachari Vasudevan

Anju Vasudevan

Ramaswami Vasudevan

 

Другие публикации лиц с тем же именем

A Skew-Normal Canonical Model for Statistical Static Timing Analysis., , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2359-2368 (2016)On the computation of criticality in statistical timing analysis., и . ICCAD, стр. 172-179. ACM, (2012)Probabilistic Error Modeling for Two-part Segmented Approximate Adders., , и . ISCAS, стр. 1-5. IEEE, (2018)An efficient algorithm for frequency-weighted balanced truncation of VLSI interconnects in descriptor form., и . DAC, стр. 187:1-187:6. ACM, (2015)A Hierarchical Technique for Statistical Path Selection and Criticality Computation., и . ACM Trans. Design Autom. Electr. Syst., 23 (1): 9:1-9:24 (2017)A Transistor Level Placement Tool for Custom Cell Generation., , , и . VLSI Design, стр. 254-257. IEEE Computer Society, (2000)Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD., и . VLSI Design, стр. 336-341. IEEE Computer Society, (2000)Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits.. DAC, стр. 397-402. ACM, (2005)Scheduling divisible loads on partially reconfigurable hardware., и . FCCM, стр. 289-290. IEEE Computer Society, (2006)An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC., и . ISCAS (1), стр. 281-284. IEEE, (2004)