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VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing., , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3136-3147 (2003)Congestion driven incremental placement algorithm for standard cell layout., , и . ASP-DAC, стр. 723-728. ACM, (2003)UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing., , , , , , и . ASP-DAC, стр. 834-839. ACM, (2003)A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints., , , и . APCCAS, стр. 792-795. IEEE, (2006)A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design., , , , и . SAMOS, том 3553 из Lecture Notes in Computer Science, стр. 344-353. Springer, (2005)Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain., , , и . J. Comput. Sci. Technol., 20 (2): 224-230 (2005)Performance-Driven Steiner Tree Algorithm for Global Routing., , , , и . DAC, стр. 177-181. ACM Press, (1993)Timing-driven global routing with efficient buffer insertion., , и . ISCAS (3), стр. 2449-2452. IEEE, (2005)Interconnect delay optimization via high level re-synthesis after floorplanning., , и . ISCAS (6), стр. 5641-5644. IEEE, (2005)Leakage power optimization for clock network using dual-Vth technology., , и . ISCAS, стр. 2769-2772. IEEE, (2008)