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MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder., , , , и . Int. J. Embed. Real Time Commun. Syst., 5 (2): 43-60 (2014)A novel architecture design for VLSI implementation of integer DCT in HEVC standard., и . Multim. Tools Appl., 79 (33-34): 23977-23993 (2020)Hardware implementation of PSO-based approximate DST transform for VVC standard., , , , и . J. Real Time Image Process., 19 (1): 87-101 (2022)Fast coding unit selection and motion estimation algorithm based on early detection of zero block quantified transform coefficients for high-efficiency video coding standard., , , и . IET Image Processing, 10 (5): 371-380 (2016)HW/SW Codesign of the H.263 Video Coder., , , , , и . CCECE, стр. 783-787. IEEE, (2006)An optimized hardware architecture of 4×4, 8×8, 16×16 and 32×32 inverse transform for HEVC., , , и . ATSIP, стр. 264-267. IEEE, (2016)An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA., , , , , и . ICECS, стр. 814-817. IEEE, (2006)Analysis of Coding and Transfer of Arien Video Sequences from H.264 Standard., , , и . ATSIP, стр. 1-5. IEEE, (2020)Perceptual Evaluation of JPEG2000., , , и . Eur. Trans. Telecommun., 15 (2): 135-143 (2004)Fast inter-prediction algorithms for spatial Scalable High efficiency Video Coding SHVC., , , и . Signal Image Video Process., 13 (1): 145-153 (2019)