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A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators.

, , , и . ISCAS, стр. 1-5. IEEE, (2020)

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John Gabriel Kauffman

Giuseppe G G Manzardo

G Lüers

G Baumann

G Schweitzer

 

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Low power quantizer design in CT Delta Sigma modulators., , , , и . ISCAS, стр. 1990-1993. IEEE, (2013)An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR., , , и . IEEE J. Solid State Circuits, 46 (12): 2869-2881 (2011)PVT robust design of wideband CT delta sigma modulators including finite GBW compensation., , и . MWSCAS, стр. 382-385. IEEE, (2012)Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators., , , , и . ISCAS, стр. 561-565. IEEE, (2022)A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS., , , , , и . IEEE J. Solid State Circuits, 57 (11): 3407-3417 (2022)Delay Error Shaping in ΔΣ Modulators Using Time-Interleaved High Resolution Quantizers., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2700-2710 (июля 2023)A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (11): 748-752 (2011)A reconfigurable Continuous-Time ΔΣ-ADC using a digitally programmable gm-C array., , , , и . MWSCAS, стр. 810-813. IEEE, (2012)A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR., , , , и . ESSCIRC, стр. 401-404. IEEE, (2023)A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI., , , , и . ESSCIRC, стр. 141-144. IEEE, (2023)