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User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis., и . ISQED, стр. 289-292. IEEE, (2015)Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)., , и . Integr., (2017)Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints., и . iNIS, стр. 1-6. IEEE, (2015)Secure Hierarchical VANETs., и . ANTS, стр. 1-5. IEEE, (2018)Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis., и . Expert Syst. Appl., 42 (10): 4719-4732 (2015)Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis., и . ACM Great Lakes Symposium on VLSI, стр. 167-172. ACM, (2015)TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (4): 655-668 (2017)Low-cost security aware HLS methodology., , и . IET Comput. Digit. Tech., 11 (2): 68-79 (2017)Detection and Prevention of Black Hole Attack in SUPERMAN., и . IEEE ANTS, стр. 1-6. IEEE, (2020)Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget., и . ICIT, стр. 345-350. IEEE, (2014)