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Exploring architecture parameters for dual-output LUT based FPGAs.

, , , , и . FPL, стр. 1-6. IEEE, (2014)

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Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

 

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Impact of capacitor array mismatch in embedded CMOS CR SAR ADC design., , , , и . Circuits, Signals, and Systems, стр. 165-168. IASTED/ACTA Press, (2005)A novel low voltage Subtracting BandGap Reference with temperature coefficient of 2.2 ppm/°., , и . ISCAS, стр. 2281-2284. IEEE, (2011)A 47-dB linear CMOS variable gain amplifier using current squaring technique., , , и . APCCAS, стр. 76-79. IEEE, (2010)Start-up analysis for differential ring oscillator with even number of stages., , , , и . APCCAS, стр. 636-639. IEEE, (2010)Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA., , , , , и . FPT, стр. 19-27. IEEE, (2019)Exploring architecture parameters for dual-output LUT based FPGAs., , , , и . FPL, стр. 1-6. IEEE, (2014)A technology mapper for depth-constrained FPGA logic cells., , , , , , , и . FPL, стр. 1-8. IEEE, (2015)An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform., , , и . SoCC, стр. 50-55. IEEE, (2019)Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs., , , , , и . ICCAD, стр. 686-693. IEEE, (2010)A semi-supervised modeling approach for performance characterization of FPGA architectures., , , , , и . FPL, стр. 1-6. IEEE, (2014)