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TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories., и . Int. J. Embed. Syst., 1 (1/2): 134-149 (2005)An efficient graph representation for arithmetic circuitverification., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (12): 1443-1454 (2001)On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication.. IEEE Trans. Computers, 40 (2): 205-213 (1991)Automatic Clock Abstraction from Sequential Circuits., , и . DAC, стр. 707-711. ACM Press, (1995)Bit-Level Analysis of an SRT Divider Circuit.. DAC, стр. 661-665. ACM Press, (1996)Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods., и . CAV, том 2725 из Lecture Notes in Computer Science, стр. 154-166. Springer, (2003)Revisiting Positive Equality., , , и . TACAS, том 2988 из Lecture Notes in Computer Science, стр. 1-15. Springer, (2004)A Performance Study of BDD-Based Model Checking., , , , , , , и . FMCAD, том 1522 из Lecture Notes in Computer Science, стр. 255-289. Springer, (1998)Modeling and Verification of Out-of-Order Microprocessors in UCLID., , и . FMCAD, том 2517 из Lecture Notes in Computer Science, стр. 142-159. Springer, (2002)SetA*: An Efficient BDD-Based Heuristic Search Algorithm., , и . AAAI/IAAI, стр. 668-673. AAAI Press / The MIT Press, (2002)