( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.

, , , , , , , и . FPGA, стр. 242-251. ACM, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Hsiang Kuang

Eugen Lai

Waltraud Lai

Mao Lai

Xin Lai

 

Другие публикации лиц с тем же именем

Accelerator design with decoupled hardware customizations: benefits and challenges: invited., , , , , , , , , и 1 other автор(ы). DAC, стр. 1351-1354. ACM, (2022)HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs., , , , , , и . FPGA, стр. 78-88. ACM, (2022)SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs., , , , , , , , , и 6 other автор(ы). ICCAD, стр. 73:1-73:9. IEEE, (2020)Asynchronous QDI Circuit Synthesis from Signal Transition Protocols., , и . ICCAD, стр. 434-441. IEEE, (2015)A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines., , и . ICCAD, стр. 736-743. IEEE, (2015)SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis., , и . ICCAD, стр. 442-449. IEEE, (2015)Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits., , и . DAC, стр. 192:1-192:6. ACM, (2014)Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits., , , и . ICCAD, стр. 5. ACM, (2016)Bring Your Own Codegen to Deep Learning Compiler., , , , , , , , и . CoRR, (2021)HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing., , , , , , , и . FPGA, стр. 242-251. ACM, (2019)