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Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors., , , и . Euro-Par, том 5704 из Lecture Notes in Computer Science, стр. 309-320. Springer, (2009)FOS: a low-power cache organization for multicores., , , и . J. Supercomput., 75 (10): 6542-6573 (2019)Power Reduction In Advanced Embedded IPC Processors., , , , и . Intell. Autom. Soft Comput., 15 (3): 495-507 (2009)Dynamic WCET Estimation for Real-Time Multicore Embedded Systems Supporting DVFS., , , , и . HPCC/CSS/ICESS, стр. 27-33. IEEE, (2014)Out-of-order retirement of instructions in sequentially consistent multiprocessors., , , , и . ICCD, стр. 1-8. IEEE Computer Society, (2010)A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions., , , , и . IEEE Trans. Parallel Distributed Syst., 23 (8): 1361-1368 (2012)A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies., , , и . J. Parallel Distributed Comput., (2017)Addressing Fairness in SMT Multicores with a Progress-Aware Scheduler., , , и . IPDPS, стр. 187-196. IEEE Computer Society, (2015)Characterizing Parallel Workloads to Reduce Multiple Writer Overhead in Shared Virtual Memory Systems., , и . PDP, стр. 261-268. IEEE Computer Society, (2002)Dynamic task set partitioning based on balancing memory requirements to reduce power consumption., , , , и . ICS, стр. 513-514. ACM, (2009)