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Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level.

, , , , , , , и . ATS, стр. 98. IEEE, (2019)

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Chia Ching Ooi

Charles Woei-Jye Yee

Hernani Tiago Yee Madeira

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Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection., , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 103-A (2): 502-509 (2020)A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1535-1544 (2008)A New Design-for-Testability Method Based on Thru-Testability., и . J. Electron. Test., 27 (5): 583-598 (2011)Machine-Learning-Based Multiple Abstraction-Level Detection of Hardware Trojan Inserted at Register-Transfer Level., , , , , , , и . ATS, стр. 98. IEEE, (2019)Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms., , , , и . FCCM, стр. 102. IEEE Computer Society, (2015)Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers., , и . FCCM, стр. 234. IEEE Computer Society, (2015)RtFog: A Real-Time FPGA-Based Fog Node With Remote Dynamically Reconfigurable Application Plane for Fog Analytics Redeployment., , и . IEEE Trans. Green Commun. Netw., 6 (1): 341-351 (2022)A New Scan Design Technique Based on Pre-Synthesis Thru Functions., и . ATS, стр. 163-168. IEEE, (2006)An FPGA-based Middlebox with Remote Dynamically Reconfigurable Application Plane., , и . TENCON, стр. 52-56. IEEE, (2021)Net Classification Based on Testability and Netlist Structural Features for Hardware Trojan Detection., , , , , , , и . ATS, стр. 105-110. IEEE, (2019)