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Double patterning layout decomposition for simultaneous conflict and stitch minimization., , и . ISPD, стр. 107-114. ACM, (2009)Overlay aware interconnect and timing variation modeling for double patterning technology., и . ICCAD, стр. 488-493. IEEE Computer Society, (2008)Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper)., , , , , , , и . ICCAD, стр. 240-242. ACM, (2012)Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner., и . ISQED, стр. 352-356. IEEE Computer Society, (2008)Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis., , , , и . ISQED, стр. 344-347. IEEE Computer Society, (2003)Chemical-mechanical polishing aware application-specific 3D NoC design., , , и . ICCAD, стр. 207-212. IEEE Computer Society, (2011)Stress-driven 3D-IC placement with TSV keep-out zone and regularity study., , , , и . ICCAD, стр. 669-674. IEEE, (2010)Layout aware line-edge roughness modeling and poly optimization for leakage minimization., и . DAC, стр. 447-452. ACM, (2011)A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography., , , , и . ASP-DAC, стр. 637-644. IEEE, (2010)TSV stress aware timing analysis with applications to 3D-IC layout optimization., , , , и . DAC, стр. 803-806. ACM, (2010)