( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition.

, , , , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2370-2383 (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

 

Другие публикации лиц с тем же именем

A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , и . A-SSCC, стр. 191-194. IEEE, (2018)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system., , , , , и . Sci. China Inf. Sci., 57 (8): 1-14 (2014)Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture., , , , , , и . Sci. China Inf. Sci., 56 (11): 1-20 (2013)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors., , , и . J. Parallel Distributed Comput., 74 (9): 2818-2830 (2014)Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1895-1908 (2016)Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms., , , и . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 3085-3098 (2015)Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , и . ISCAS, стр. 2541-2544. IEEE, (2013)Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , и . ISCAS, стр. 1-4. IEEE, (2017)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , и . DAC, стр. 64:1-64:6. ACM, (2016)