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Distributed Control Independence for Composable Multi-processors.

M. Mao, H. An, T. Sun, Q. Li, B. Deng, X. Wei, и J. Zhou. ACIS-ICIS, стр. 124-129. IEEE Computer Society, (2012)

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Tongsheng Mao

Yiqin Mao

Ning-hui Mao

Lei Mao

Zhengrong Mao

Другие публикации лиц с тем же именем

Distributed replay protocol for distributed uniprocessors.M. Mao, H. An, B. Deng, T. Sun, X. Wei, W. Zhou, и W. Han. ICS, стр. 3-14. ACM, (2012)Exploring Applications of STT-RAM in GPU Architectures.X. Liu, M. Mao, X. Bi, H. Li, и Y. Chen. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 238-249 (2021)CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.W. Wen, M. Mao, X. Zhu, S. Kang, D. Wang, и Y. Chen. ICCAD, стр. 1-8. IEEE, (2013)FACRA: Flexible-Core Architecture Chip Resource Abstractor.T. Sun, H. An, Y. Ren, M. Mao, Y. Liu, M. Xu, и Q. Li. PDCAT, стр. 440-447. IEEE Computer Society, (2010)An efficient STT-RAM-based register file in GPU architectures.X. Liu, M. Mao, X. Bi, H. Li, и Y. Chen. ASP-DAC, стр. 490-495. IEEE, (2015)TEMP: thread batch enabled memory partitioning for GPU.M. Mao, W. Wen, X. Liu, J. Hu, D. Wang, Y. Chen, и H. Li. DAC, стр. 65:1-65:6. ACM, (2016)Heterogeneous systems with reconfigurable neuromorphic computing accelerators.S. Li, X. Liu, M. Mao, H. Li, Y. Chen, B. Li, и Y. Wang. ISCAS, стр. 125-128. IEEE, (2016)TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.Z. Liu, M. Mao, T. Liu, X. Wang, W. Wen, Y. Chen, H. Li, D. Wang, Y. Pei, и N. Ge. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (10): 1985-1998 (2018)Prefetching techniques for STT-RAM based last-level cache in CMP systems.M. Mao, G. Sun, Y. Li, A. Jones, и Y. Chen. ASP-DAC, стр. 67-72. IEEE, (2014)Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.M. Mao, W. Wen, Y. Zhang, Y. Chen, и H. Li. DAC, стр. 196:1-196:6. ACM, (2014)

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