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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture., , и . IEEE J. Solid State Circuits, 41 (12): 2650-2657 (2006)Test Generation for Weak Resistive Bridges., , и . ATS, стр. 265-272. IEEE, (2006)BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level., и . Asian Test Symposium, стр. 244-252. IEEE Computer Society, (1998)Design and test of latch-based circuits to maximize performance, yield, and delay test quality., и . ITC, стр. 94-103. IEEE Computer Society, (2010)Switch-level delay test of domino logic circuits., , и . ITC, стр. 367-376. IEEE Computer Society, (2001)ERTG: A test generator for error-rate testing., и . ITC, стр. 1-10. IEEE Computer Society, (2007)Optimizing redundancy design for chip-multiprocessors for flexible utility functions., и . ITC, стр. 1-8. IEEE Computer Society, (2014)Analysis of Ground Bounce in Deep Sub-Micron Circuits., , и . VTS, стр. 110-116. IEEE Computer Society, (1997)A New March Test for Process-Variation Induced Delay Faults in SRAMs., , , , , , и . Asian Test Symposium, стр. 115-122. IEEE Computer Society, (2013)Efficient Trojan Detection via Calibration of Process Variations., и . Asian Test Symposium, стр. 355-361. IEEE Computer Society, (2012)