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10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS.

, , и . ISSCC, стр. 1-3. IEEE, (2015)

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Kiarash Fatehi

Kiarash Narimani

Kiarash Mahdavi

Kiarash Fatehi

Kiarash Karampour

 

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A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS., , и . NEWCAS, стр. 1-4. IEEE, (2016)10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS., , и . ISSCC, стр. 1-3. IEEE, (2015)A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET., , , , , , , , , и 20 other автор(ы). VLSI Circuits, стр. 92-. IEEE, (2019)A Method for Noise Reduction in Active-RC Circuits., и . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (12): 906-910 (2011)A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS., , и . VLSIC, стр. 180-. IEEE, (2015)A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (12): 1387-1391 (2017)An Orthogonal Pulse Amplitude Modulation Signaling for High-Speed Wireline Communications., и . ISCAS, стр. 1-5. IEEE, (2023)Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ., , , , , , , , , и 11 other автор(ы). CICC, стр. 1-8. IEEE, (2020)