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publications

(17)

• Mpeg2 Video Encoding in Consumer Electronics.
  Richard P. Kleihorst and Albert van der Werf and W. H. A. Brüls and Wim F. J. Verhaegh and E. Waterlander VLSI Signal Processing 17 241-253 (1997)
  to dblp by dblp on 2008-08-07 00:00:00
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• A general-purpose signal processor architecture for neurocomputing and preprocessing applications.
  Ulrich Ramacher and Jörg Beichter and Nico Brüls VLSI Signal Processing 6 45-56 (1993)
  to dblp by dblp on 2008-08-07 00:00:00
  | URL | BibTeX  
• Enabling Introduction of Stereoscopic (3D) Video: Formats and Compression Standards.
  W. H. A. Bruls and Chris Varekamp and Rene Klein Gunnewiek and Bart Barenbrug and Amaud Bourge ICIP (1) 89-92 (2007)
  to dblp by dblp on 2008-06-25 00:00:00
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• Utilizing HDTV Displays to its Full Potential and its Impact on Video Compression.
  A. A. S. Sluyterman and W. H. A. Bruls ICIP (1) 29-32 (2007)
  to dblp by dblp on 2008-06-25 00:00:00
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• Bridging Defects Resistance Measurements in a CMOS Process.
  Rosa Rodríguez-Montañés and Joan Figueras and Eric Bruls ITC 892-899 (1992)
  to dblp by dblp on 2006-06-26 00:00:00
  | URL | BibTeX  
• 100 GOPS vision processor for automotive applications.
  Ulrich Ramacher and Nico Brüls and J. A. Ulrich Hachmann and Jens Harnisch and Wolfgang Raab and Axel Techmer SIGARCH Computer Architecture News 31 60-68 (2003)
  to dblp by dblp on 2006-04-06 00:00:00
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• Multiprocessor And Memory Architecture Of The Neurocomputer Synapse-1.
  Ulrich Ramacher and Wolfgang Raab and Joachim K. Anlauf and J. A. Ulrich Hachmann and Jörg Beichter and Nico Brüls and Matthias Wesseling and Elisabeth Sicheneder and Reinhard Männer and Joachim Gläß and Andreas Wurz Int. J. Neural Syst. 4 333-336 (1993)
  to dblp by dblp on 2006-01-03 00:00:00
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• SYNAPSE-1: a high-speed general purpose parallel neurocomputer system.
  Ulrich Ramacher and Wolfgang Raab and J. A. Ulrich Hachmann and Jörg Beichter and Nico Brüls and Matthias Wesseling and Elisabeth Sicheneder and Joachim Gläß and Andreas Wurz and Reinhard Männer IPPS 774-781 (1995)
  to dblp by dblp on 2005-12-01 00:00:00
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• A 100-GOPS Programmable Processor for Vehicle Vision Systems.
  Wolfgang Raab and Nico Brüls and J. A. Ulrich Hachmann and Jens Harnisch and Ulrich Ramacher and Christian Sauer and Axel Techmer IEEE Design & Test of Computers 20 8-16 (2003)
  to dblp by dblp on 2004-11-08 00:00:00
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• A holistic methodology for network processor design.
  Olaf Bonorden and Nikolaus Brüls and Uwe Kastens and Dinh Khoi Le and Friedhelm Meyer auf der Heide and Jörg-Christian Niemann and Mario Porrmann and Ulrich Rückert and Adrian Slowik and Michael Thies LCN 583- (2003)
  to dblp by dblp on 2003-11-14 00:00:00
  | URL | BibTeX