%0 Journal Article %1 journals/jssc/DengYUSKOM15 %A Deng, Wei %A Yang, Dongsheng %A Ueno, Tomohiro %A Siriburanon, Teerachot %A Kondo, Satoshi %A Okada, Kenichi %A Matsuzawa, Akira %D 2015 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 68-80 %T A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. %U http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#DengYUSKOM15 %V 50

@article{journals/jssc/DengYUSKOM15, added-at = {2022-09-07T00:00:00.000+0200}, author = {Deng, Wei and Yang, Dongsheng and Ueno, Tomohiro and Siriburanon, Teerachot and Kondo, Satoshi and Okada, Kenichi and Matsuzawa, Akira}, biburl = {https://www.bibsonomy.org/bibtex/23a9f49e02bca7c27041e22188c1adbfd/dblp}, ee = {https://doi.org/10.1109/JSSC.2014.2348311}, interhash = {08e073a68a133be76c8e5316031adc5c}, intrahash = {3a9f49e02bca7c27041e22188c1adbfd}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {68-80}, timestamp = {2024-04-08T10:44:28.000+0200}, title = {A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc50.html#DengYUSKOM15}, volume = 50, year = 2015 }