%0 Journal Article %1 RGowtham_2015 %A Mr.R.Gowtham, %A Mr.V.Govindaraj, %D 2015 %I Auricle Technologies, Pvt., Ltd. %J International Journal on Recent and Innovation Trends in Computing and Communication %K Graph Registers SPI Scenario Trek interface model serial %N 3 %P 1513--1516 %R 10.17762/ijritcc2321-8169.1503134 %T Generation of Graph For Serial Peripheral Interface Verification %U http://dx.doi.org/10.17762/ijritcc2321-8169.1503134 %V 3 %X With the rapid strides in Semiconductor processing technologies, the density of transistors on the die is increasing in line with Moore’s law which in turn is increasing the complexity of the whole SOC (System on Chip) design. With manufacturing yield and time-to-market schedules crucial SOC, it is important to select verification and analysis solutions that offer the best possible performance, while minimizing iteration time and data volume. The main objective is to verify SERIAL PERIPHERAL INTERFACE using graph based scenario model. This technique includes generation of graph of APB_WB (Advanced Peripheral Bus Wishbone) and integration of test cases generated by the graph to APB. The graph is generated by the software Trek. This software automatically generates test cases which are self-verifying. The test cases generated from graph?based scenario model captures intended system behavior. Trek takes input information from scenario models describing the desired outcomes, developed by the user.

@article{RGowtham_2015, abstract = {With the rapid strides in Semiconductor processing technologies, the density of transistors on the die is increasing in line with Moore’s law which in turn is increasing the complexity of the whole SOC (System on Chip) design. With manufacturing yield and time-to-market schedules crucial SOC, it is important to select verification and analysis solutions that offer the best possible performance, while minimizing iteration time and data volume. The main objective is to verify SERIAL PERIPHERAL INTERFACE using graph based scenario model. This technique includes generation of graph of APB_WB (Advanced Peripheral Bus Wishbone) and integration of test cases generated by the graph to APB. The graph is generated by the software Trek. This software automatically generates test cases which are self-verifying. The test cases generated from graph?based scenario model captures intended system behavior. Trek takes input information from scenario models describing the desired outcomes, developed by the user.}, added-at = {2015-08-13T07:14:25.000+0200}, author = {Mr.R.Gowtham and Mr.V.Govindaraj}, biburl = {https://www.bibsonomy.org/bibtex/244db2bad1107dfeb463dded4b123f50b/ijritcc}, doi = {10.17762/ijritcc2321-8169.1503134}, interhash = {08f2ec50487b547b2aeedd784ebdf067}, intrahash = {44db2bad1107dfeb463dded4b123f50b}, journal = {International Journal on Recent and Innovation Trends in Computing and Communication}, keywords = {Graph Registers SPI Scenario Trek interface model serial}, month = {march}, number = 3, pages = {1513--1516}, publisher = {Auricle Technologies, Pvt., Ltd.}, timestamp = {2015-08-13T07:14:25.000+0200}, title = {Generation of Graph For Serial Peripheral Interface Verification}, url = {http://dx.doi.org/10.17762/ijritcc2321-8169.1503134}, volume = 3, year = 2015 }